As a technique of reducing the on resistance of a power MOSFET, a MOSFET of a trench MOS structure is known. This MOSFET of the trench MOS structure has a plurality of trenches in a semiconductor layer at predetermined intervals. The semiconductor layer serves as a channel area. In an inner wall of this trench, an insulation film which serves as a gate insulation film is formed, and a conductive layer which serves as a gate electrode is embedded in the trench via this insulation film. By miniaturizing the width of this trench and width of the semiconductor layer between the trenches, it is possible to increase the channel density in an element.
A structure is known in which a schottky barrier diode (SBD) is formed using this trench MOS structure. Further, a Merge PIN Schottky (MPS) structure is known as another structure, and uses a P type diffusion layer instead of a trench MOS. The SBD using the above trench MOS structure provides a withstand voltage at an epitaxial ratio resistance lower than in the MPS structure, and consequently, can provide an advantage that a forward voltage drop is low. Further, upon a reverse bias, by expanding a depletion layer between trenches, it is possible to withstand a reverse bias voltage.
However, while a schottky barrier diode using the trench MOS structure has a small on resistance upon a forward bias, the schottky barrier diode has a problem in that a leak current is great upon application of a reverse bias. Although it is possible to suppress a leak current by decreasing the interval between trenches, in this case, there is a problem in that a forward voltage upon a forward bias increases and the on resistance increases.
Hence, a schottky barrier diode is demanded which can suppress an increase of the leak current upon a reverse bias while maintaining a small on resistance upon a forward bias.